1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various embodiments of a combination FinFET/Ultra-Thin Body (UTB) transistor device and various methods of making such devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semi-conductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Typically, a high performance integrated circuit product, such as a high performance microprocessor, will contain billions of individual field effect transistors (FETs). The transistors are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region of the transistor. The transistor devices come in a variety of forms, e.g., so-called planar transistor devices, 3D or FinFET devices, ultra-thin body (UTB) devices, etc.
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device 10 includes a plurality of trenches 14 that define three illustrative fins 16, a gate structure 18, sidewall spacers 20 and a gate cap layer 22. FIG. 1B is a cross-sectional view of the FinFET device 10 taken through the gate structure 18 in a gate width direction of the device 10. The gate structure 18 is typically comprised of a layer of gate insulating material 18A (see FIG. 1B), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode 18B (see FIG. 1B) for the device 10. The fins 16 have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L of the fins 16 corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 16 covered by the gate structure 18 are the channel regions of the FinFET device 10. In a conventional process flow, the portions of the fins 16 that are positioned outside of the spacers 20, i.e., in the source/drain regions of the device 10, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes. In the FinFET device, the gate structure 18 may enclose both the sides and the upper surface of all or a portion of the fins 16 to form a tri-gate structure, i.e., a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer (not shown), e.g., silicon nitride, is positioned at the top of the fins 16 and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate 12 so as to reduce the physical size of the semiconductor device. The gate structures 18 for such FinFET devices 10 may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques. Although the FinFET device 10 is a superior structure as compared to a planar transistor device, it does have some limitations. For example, with reference to FIG. 1B, the height of the fins 16 covered by the isolation material 24, as indicated by the dimension 16×, is effectively wasted and does not make any contribution to the drive current of the device 10.
FIG. 1C is a simplistic cross-sectional view of an illustrative UTB device 30 that is formed above a substrate 12. In general, the UTB device 30 is comprised of a layer of insulation material 32, a very thin (e.g., up to 15 nm or so) active semiconductor layer 34, a gate insulation layer 36, a gate electrode 38, sidewall spacers 39, a gate cap layer 40 and illustrative raised source/drain regions 42.
What is needed for future integrated circuit products is a new transistor structure that provides a relatively high drive current per area of substrate used to make the device, i.e., a higher drive current density that may be readily manufactured in a high-volume VLSI production environment. The present disclosure is directed to various embodiments of a combination FinFET/Ultra-Thin Body (UTB) transistor device and various methods of making such devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.